A Real Time Image Processing Subsystem: GEZGIN

In this study, a real-time image processing subsystem, GEZGIN, which is currently being developed for BILSAT-1, a 100kg class micro-satellite, is presented. BILSAT-1 is being constructed in accordance with a technology transfer agreement between TÜBITAK-BILTEN (Turkey) and SSTL (UK) and planned to be placed into a 650 km sunsynchronous orbit in Summer 2003. GEZGIN is one of the two Turkish R&D payloads to be hosted on BILSAT-1. One of the missions of BILSAT-1 is constructing a Digital Elevation Model of Turkey using both multi-spectral and panchromatic imagers. Due to limited down-link bandwidth and on-board storage capacity, employment of a realtime image compression scheme is highly advantageous for the mission. GEZGIN has evolved as an implementation to achieve image compression tasks that would lead to an efficient utilization of both the down-link and on-board storage. The image processing on GEZGIN includes capturing of 4-band multi-spectral images of size 2048x2048 8- bit pixels, compressing them simultaneously with the new industry standard JPEG2000 algorithm and forwarding the compressed multi-spectral image to Solid State Data Recorders (SSDR) of BILSAT-1 for storage and down-link transmission. The mission definition together with orbital parameters impose a 6.5 seconds constraint on real-time image compression. GEZGIN meets this constraint by exploiting the parallelism among image processing units and assigning compute intensive tasks to dedicated hardware. The proposed hardware also allows for full reconfigurability of all processing units

Podwójne znakowanie immunologiczne CD133 i Ki-67 wskazuje na ich istotną współlokalizację w podtypie włóknistym oponiaków

Background and purpose A unique molecular and/or cellular marker for meningiomas, the most common intracranial tumours, has not been identified yet. Material and methods We investigated the co-localization fraction of CD133/Ki-67 in meningioma tissue array slide composed of 80 meningioma tissue samples of various histological variants. CD133 – a cell membrane stem cell marker – was previously proved to be associated with the initiation and progression of intracerebral gliomas and medulloblastomas. Results Immunohistochemical co-localization of CD133/Ki-67 was significantly higher in fibroblastic variant than in meningothelial and transitional subtypes. However, since there were only 3 atypical and 1 malignant meningioma spots in the tumour tissue array slide, it is difficult to draw a firm conclusion regarding the actual co-localization percentage and persistence of CD133/Ki-67 in atypical and malignant meningiomas. Conclusions Far higher co-staining percentage of CD133/Ki-67 in fibroblastic meningioma samples compared to meningothelial subtype, a histological meningioma variant, architectonically resembling the non-neoplastic meningeal cells, gave us the impression that CD133 may play a role in the formation and progression of fibroblastic meningioma variants. The persistency and the validity of this finding need to be verified by further histopathological and molecular research in order to clarify the possible role of CD133 in meningiogenesis.Wstęp i cel pracy Nie określono dotąd unikalnego znacznika molekularnego lub komórkowego dla oponiaków, najczęstszych guzów wewnątrzczaszkowych. Wcześniej wykazano, że CD133 – znacznik błony komórkowej komórek macierzystych – jest związany z zapoczątkowaniem, a także wzrostem wewnątrzczaszkowych glejaków i rdzeniaków płodowych. Materiał i metody Zbadano odsetek współlokalizacji CD133/Ki-67 w zestawach macierzy tkankowych oponiaków, złożonych z próbek 80 rozmaitych odmian histologicznych oponiaków. Wyniki Immunohistochemiczna współlokalizacja CD133 i Ki-67 była stwierdzana istotnie częściej w podtypie włóknistym oponiaka niż w podtypach meningotelialnym lub przejściowym. Ze względu na małą liczbę preparatów opo-niaków atypowych (3) oraz złośliwych (1) w badanej macierzy tkankowej trudno wyciągnąć jednoznaczne wnioski dotyczące rzeczywistego odsetka współlokalizacji i utrzymywania się CD133/Ki-67 w oponiakach atypowych i złośliwych. Wnioski Znacząco większy odsetek wspólnie występującej reaktywności CD133/Ki-67 w preparatach oponiaka włóknistego w porównaniu z podtypem meningotelialnym, którego architektonika przypomina nienowotworowe komórki opon, sprawia wrażenie, że CD133 może odgrywać rolę w powstawaniu i rozwoju oponiaków włóknistych. Trafność tego spostrzeżenia wymaga weryfikacji w dalszych badaniach histopatologicznych i molekularnych w celu wyjaśnienia możliwej roli CD133 w powstawaniu oponiaków

Low-power design of a 64-tap, 4-bit Digital Matched Filter using Systolic Array architecture and CVSL circuit techniques in CMOS

A 4-bit 64-chip Pseudo Noise (PN) coded Digital Matched Filter (DMF) is designed in 0.7um CMOS technology using Systolic Array (SA) architecture. Full-custom and full-static Cascode Voltage Switch Logic (CVSL) circuit techniques have been employed in the implementation of the basic building blocks (systoles) of the SA DMF. Significant reduction in number of transistors and power consumption have been achieved. The resultant IC is to be used at the receiver side of a wireless Direct Sequence Spread Spectrum (DSSS) communication system

Design of a fully-static differential low-power CMOS flip-flop

A fully-static flip-flop structure is proposed and compared to both the conventional CMOS flip-flop and the Cascode Voltage Switch Logic (CVSL) static flip-flop proposed by Yuan and Svensson [1], in terms of speed, power consumption and silicon area. Then an add-and-delay circuit is implemented using all three flip-flop structures to demonstrate the performance of the proposed flip-flop. The add-and-delay structure is chosen since it is a widely used block in digital signal processing. The proposed structure showed to be consuming less power and occupying smaller silicon area. It has the additional advantage of being easier to merge with pass-transistor logic structures

Low-power Design of a Digital FM Demodulator based

A digital FA4 receiver/demodulator system, utilizing the zero-cross detection technique [l]> is designed and implemented on a single IC. Zero-cross detection is performed at an IF frequency of 455 kHz. The system is simulated for BT=0.3 GMSK input with an input data rate of 8000 bps and displayed a better BER Performance than coherent detectors. The developed system is implemented in 0.5 pm triple-metal standard digital CMOS technology. Power dissipation of the resultant IC is less than its analog counterparts while the occupied silicon area is very small making it low cost. The FM receiver/demodulator IC is suitable to be used in low-power and low-cost mobile communication applications providing better BER performance than conventional systems. especially in noisy channels. 1

A real time, low latency, hardware implementation of the 2-D discrete wavelet transformation for streaming image applications

In this paper, we present a 2-D Discrete Wavelet Transformation (DWT) hardware for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n(1) x n(2) size image processed using (n(1)/k(1)) x (n(2)/k(2)) sized tiles the latency is equal to the time elapsed to accumulate a (1/k(1)) portion of one image. In addition, a (2/k(1)) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a Low Earth Orbit (LEO) micro-satellite, which will be launched in August 2003

A real time, low latency, FPGA implementation of the 2-D discrete wavelet transformation for streaming image applications

In this paper, we present an architecture and a hardware implementation of the 2-D Discrete Wavelet Transformation (DWT) for applications where row-based raw image data is streamed in at high bandwidths and local buffering of the entire image is not feasible. The architecture is especially suited for multi-spectral imager systems, such as on board an imaging satellite, however can be used in any application where time to next image constraints require real-time processing of multiple images. The latency that is introduced as the images stream through the DWT filter and the amount of locally stored image data is a function of the image and tile size. For an n(1) x n(2) size image processed using (n(1)/k(1)) x (n(2)/k(2)) sized tiles the latency is equal to the time elapsed to accumulate a (1/k(1)) portion of one image. In addition, a (2/k(1)) portion of each image is buffered locally. The proposed hardware has been implemented on an FPGA and is part of a JPEG2000 compression system designed as a payload for a Low Earth Orbit (LEO) micro-satellite, which will be launched in August 2003

GOLGE: A case study of a secure data communication subsystem for micro-satellites

This paper presents a real-time data encryption/decryption subsystem developed for a satellite, which is planned to be launched in 2007 by TUBITAK-BILTEN. The subsystem GOLGE contains two ASICs, which perform encryption/decryption using AES (Advanced Encryption Standard) and RSA (Rivest-Shamir-Adleman) algorithms and a communication interface unit. The data/command interface of the GOLGE module is implemented on a reconfigurable ASIC (FPGA), where the encryption/decryption processors have previously been designed in TUBITAK-BILTEN and prototyped in AMIS 0.35-mu m CMOS technology. The system uses an 8-bit bidirectional data bus, which operates at a maximum frequency of 40MHz supplying a throughput of 160 Mbit/sec and a SpaceWire interface, which provides a 100 Mbit/sec serial data communication link

GEZGIN-2: An advanced image processing subsystem for earth-observing small satellites

GEZGIN-2 is a real-time image processing subsystem, currently being developed for RASAT, the second small satellite to be launched by TUBITAK-BILTEN, in 2007. It is an advanced version of the GEZGIN payload, implementing JPEG 2000 image compression algorithm and currently flying on the BILSAT-1 satellite. The main enhancements in GEZGIN-2 are the integration of the full processing path of JPEG 2000 algorithm in a single Field Programmable Gate Array (FPGA) for increased processing performance and high speed data links complying with the ESA Spacewire standard, for data transfer at a rate of 100 Mbps. In addition to JPEG2000, GEZGIN-2 facilitates image pre-processing for cloud/sea detection and image/data encryption implemented on a daughter-board called GOLGE. As in GEZGIN, GEZGIN-2 allows for adjustment of compression ratio for different mission times by means of run-time supplied parameters and full reconfigurability in orbit